1. Field of the Invention
The present invention relates to a differential amplifying circuit. More specifically, the present invention relates to a differential amplifying circuit utilizing MOS transistors having a large amplification factor and a quick transient response rate.
2. Description of the Prior Art
FIG. 1 shows a conventional circuit of this type. Referring to the figure, the reference characters D1 and D1 are complementary inputs, the reference characters D2 and D2 are complementary outputs, the reference numeral 1 denotes a voltage source of normally about 5 V, the reference characters 2a and 2b denote depletion type load MOS transistors, the reference characters 3a and 3b denote enhancement type cross-connected MOS transistors, and the reference characters 4a and 4b denote enhancement type driver MOS transistors. The transistors 2a, 3a and 4a and the transistors 2b, 3b and 4b are each connected in series between the voltage source and the ground, whereby a pair of main amplifying circuits 5a and 5b of three inputs are formed.
The outputs D2 and D2 of the pair of the main amplifying circuits 5a and 5b are connected in a crossing feedback fashion to the gates of the transistors 3b and 3a.
The other four inputs of the main amplifying circuits are connected such that the input D1 is connected to the gates of the transistors 2a and 4b and the input D1 is connected to the gates of the transistors 2b and 4a. The pair of the main amplifying circuits constitute as a whole a differential main amplifying circuit with the inputs D1 and D1 as the inputs thereof and with the outputs D2 and D2 as the outputs thereof.
Now an operation thereof will be described. First let it be assumed that the high level voltage is applied to the input D1 and the low level voltage is applied to the input D1. In the main amplifying circuit 5a, the gate voltage D1 of the load transistor 2a is the low level and a current supply capability is small, while the gate voltage D1 of the driver transistor 4a is the high level and a current drive capability is large, whereby the output D2 becomes the low level voltage. Conversely, in the main amplifying circuit 5b, the gate voltage D1 of the load transistor 2b is the high level and a current supply capability is large, while the gate voltage D1 of the driver transistor 4b is the low level and a current drive capability is small, whereby the output D2 becomes the high level. Furthermore, since the outputs D2 and D2 are supplied to the gates of the transistors 3a and 3b so that the same are fed back, the amplification factor is increased and a constant amplification factor and a constant output level are attained for a broad range of the input level.
FIG. 2 shows another conventional circuit of this type, which is different from the FIG. 1 circuit. Referring to FIG. 2, the outputs D2 and D2 are inputted in a feedback fashion to the gates of the load transistors 2a and 2b.
Since the conventional differential amplifying circuits are implemented only with a pair of three-input main amplifying circuits 5a and 5b, as described in the foregoing, it is necessary to connect the inputs D1 and D1 to the gates of the load transistors 2a and 2b or to supply the outputs D2 and D2 in a feedback fashion; however, the former case involves a disadvantage that the amplification factor is small and the output of the high level voltage as high as approximately the source voltage cannot be obtained when the input voltage is low, whereas the latter case involves a disadvantage that a transient response rate in the case where the input signal changes is slow.